Founding Note: The Thousand-Fold Gap
Published March 2026
The Problem
A single NVIDIA H100 GPU draws 700 watts at peak load. A rack of eight consumes 5,600 watts. A data center filled with thousands of them demands its own power substation. In 2024, global data centers consumed approximately 415 terawatt-hours of electricity — about 1.5% of all electricity generated on Earth — and the International Energy Agency projects this will more than double to 945 TWh by 2030, driven overwhelmingly by AI workloads.
Meanwhile, the human brain — processing visual scenes, coordinating motor functions, maintaining memories, and running language comprehension simultaneously — operates on roughly 20 watts. That is not a metaphor. It is a measurement. The brain achieves this through approximately 86 billion neurons communicating via sparse, asynchronous electrical pulses called spikes, with only a small fraction of neurons active at any given moment.
The efficiency ratio is staggering. Research from the Blue Brain Project estimates that biological neural computation is approximately 900 million times more energy-efficient than current artificial computing architectures. Even accounting for differences in task complexity, the gap is at minimum three orders of magnitude.
Why This Matters Now
Three converging pressures make this gap unsustainable:
1. The Power Wall. AI model sizes are doubling every few months, but chip power efficiency improves at roughly 1.4× per generation. We are building larger models faster than we can make them cheaper to run. The U.S. share of electricity devoted to data centers may triple from 4.4% to 12% by 2028.
2. The Edge Imperative. Autonomous vehicles, industrial robots, wearable medical devices, and IoT sensors all need real-time AI inference — but they cannot carry a 700-watt GPU and a cooling system. Edge AI demands milliwatt-scale processing that responds in microseconds, not milliseconds. SynSense's Speck chip has demonstrated face recognition at under 1 milliwatt with 3.36 microsecond spike latency — proving the paradigm works.
3. The Architecture Mismatch. Conventional chips process information through dense, synchronous clock cycles — every transistor switches every cycle, whether it has useful work or not. Biological neurons fire only when they have something to communicate. This event-driven sparsity is not a minor optimization; it is a fundamentally different computational paradigm.
What Cmospike Will Study
Our research focuses on spiking neural network (SNN) chip architectures built on mature CMOS process nodes. We chose this intersection deliberately:
- Spike encoding: How should analog signals from the real world — light, sound, pressure, temperature — be efficiently converted into temporal spike patterns that preserve information while minimizing energy? Current rate-coding approaches waste most of the theoretical efficiency advantage.
- On-chip learning: Backpropagation requires global error signals propagated through every layer — expensive in time, memory, and power. Biological synapses learn through local rules like spike-timing-dependent plasticity (STDP). Can hardware implementations of local learning rules match backpropagation accuracy for edge inference tasks?
- Hybrid integration: Pure neuromorphic chips excel at specific tasks but struggle with general control flow. How should SNN accelerators interface with conventional CMOS logic (RISC-V cores, standard peripherals) in a practical system-on-chip? Zhejiang University's Darwin3 chip — supporting 2.35 million neurons alongside a RISC-V management core — provides an instructive case study.
- Process node economics: Cutting-edge chip fabrication (3nm, 5nm) costs billions in tooling and yields diminishing returns for neuromorphic workloads where transistor density matters less than interconnect flexibility. Mature nodes like 28nm and 65nm offer 10-50× lower per-wafer cost. We study which architectural innovations unlock neuromorphic efficiency on accessible process technologies.
Our Approach
Cmospike is a research entity within the PRIMSEED matrix. We do not fabricate chips. We analyze, model, and publish.
Our work products are architecture analyses, benchmark comparisons, and design-space explorations that map the frontier between biological efficiency and silicon manufacturability. We believe the most valuable contribution at this stage is not another chip, but a clearer map of the design space — so that when the next generation of neuromorphic architects sits down at their workstations, they know which trade-offs matter and which don't.
We are not promising to build the future of computing. We are studying why the present architecture is running into a wall, and where the cracks are widest.
About Cmospike
Cmospike (芯脉) is a neuromorphic chip architecture research entity within the PRIMSEED matrix. We study how spiking neural network designs — built on proven CMOS fabrication processes — can close the energy efficiency gap between artificial and biological computation.
Our Name
CMOS — Complementary Metal-Oxide Semiconductor, the dominant chip fabrication technology for over four decades. Spike — the fundamental unit of communication in biological neural networks. Our name reflects our thesis: the next leap in computing efficiency will come from rethinking how mature silicon processes represent and transmit information.
Our Place in the Matrix
| Entity | Role | |--------|------| | PRIMSEED | The seed — incubation and strategy | | ASIBeyond | The beyond — superintelligence transition research | | BioSove | The solver — biological computing accessibility | | Cmospike | The pulse — neuromorphic chip architecture |
Each PRIMSEED entity addresses a different frontier of the intelligence problem. Cmospike provides the hardware perspective: if software intelligence scales indefinitely, what physical substrate can sustain it?
Methodology
We publish architecture analyses, not chips. Our research process:
1. Survey — Map the current landscape of neuromorphic designs (Intel Loihi 2, BrainChip Akida, SynSense Speck, Zhejiang Darwin3) 2. Model — Simulate energy-performance trade-offs across process nodes, neuron models, and learning rules 3. Analyze — Identify which design decisions yield the largest efficiency gains per dollar of fabrication cost 4. Publish — Release findings as research notes accessible to engineers, investors, and policymakers
Contact
Research inquiries: research@cmospike.com
Part of the PRIMSEED research matrix.
Reach Out
For Researchers If you work on spiking neural networks, neuromorphic architectures, or CMOS process optimization, we welcome collaboration proposals and paper discussions.
For Hardware Teams Evaluating neuromorphic accelerators for your product? We offer architecture assessments and design-space analysis to help teams navigate the SNN chip landscape.
For Industry & Policy The neuromorphic computing space is evolving rapidly. We provide landscape reports and technology readiness assessments.
Use the contact form below. We read every message and typically respond within one business week.
Active Research
Spike Encoding Benchmark
Status: In Progress
How should real-world signals — images, audio, sensor data — be translated into spike trains for neural computation? The choice of encoding scheme fundamentally determines the efficiency ceiling of any SNN system. This project benchmarks rate coding, temporal coding, and population coding approaches across standardized inference tasks on 28nm and 65nm CMOS targets.
Metrics:
- Energy per inference (pJ/operation)
- Encoding latency (clock cycles to first spike)
- Information retention vs. spike sparsity trade-off
- For which task categories does STDP achieve competitive accuracy?
- What is the silicon area overhead of on-chip STDP vs. storing pre-trained weights?
- Can hybrid approaches (backpropagation for training, STDP for fine-tuning) offer the best trade-off?
- SNN accelerator as peripheral (memory-mapped, DMA-driven)
- Tightly coupled SNN-CPU with shared cache
- Disaggregated chiplet approach (SNN die + logic die)
Benchmark framework under development.
STDP vs. Backpropagation for Edge Learning
Status: Scoping
Spike-timing-dependent plasticity (STDP) is biology's learning rule. Backpropagation is deep learning's. Can STDP — implemented directly in CMOS circuits — replace backpropagation for on-chip learning at the edge? This project compares the two approaches on inference accuracy, silicon area, and power consumption for targeted edge workloads.
Research questions:
Hybrid Integration Methodology
Status: Early Research
Neuromorphic accelerators don't replace conventional processors — they augment them. This project develops design methodologies for integrating SNN accelerator blocks into conventional CMOS SoC architectures, addressing the bus interface, memory hierarchy, and workload partitioning challenges.
Target architectures:
Power Wall Literature Survey
Status: Complete
A comprehensive review of the energy efficiency limits of conventional von Neumann architectures for neural network inference, establishing the theoretical and practical motivation for spike-based alternatives. This survey covers 150+ papers spanning CMOS scaling trends, memory wall analysis, and neuromorphic architecture proposals.
Available as internal reference document.
Spike Encoding: The First Bottleneck
Technical Note — March 2026
The Problem
Before a spiking neural network can process anything, real-world data must be converted into spike trains. This encoding step is the first — and often most overlooked — bottleneck in neuromorphic system design.
Consider an image classification task. A conventional CNN processes the image as a matrix of pixel intensities. An SNN must first convert those intensities into sequences of precisely timed electrical impulses. The choice of how to do this conversion determines the upper bound on the system's energy efficiency, latency, and accuracy.
Three Encoding Paradigms
Rate Coding The simplest approach: higher pixel intensity = higher spike frequency. A bright pixel fires often; a dark pixel fires rarely. It's intuitive, robust, and wasteful — because it requires long observation windows to distinguish firing rates, and the redundant spikes consume energy.
Typical metrics on 65nm CMOS:
- Energy: ~50 pJ per pixel per inference
- Latency: 100-500 time steps
- Accuracy: Within 2% of ANN baseline on MNIST
- Energy: ~5 pJ per pixel per inference (10x improvement)
- Latency: 10-50 time steps
- Accuracy: Within 5% of ANN baseline (degrades on complex tasks)
Temporal Coding Information is encoded in the precise timing of individual spikes, not their frequency. A bright pixel fires first; a dark pixel fires last. This is dramatically more efficient — each neuron fires at most once — but requires precise timing circuits and is sensitive to process variation in analog CMOS.
Typical metrics on 65nm CMOS:
The Trade-Off Space
No encoding scheme dominates across all metrics. The choice depends on the deployment target:
| Scenario | Best Encoding | Why | |----------|--------------|-----| | Always-on sensor (IoT) | Temporal | Minimum energy per inference is critical | | Real-time classification | Rate | Robustness matters more than efficiency | | Edge learning | Population | Gradients are better defined for learning rules |
This is the core insight driving our benchmark project: there is no universal best encoding. The right choice is application-specific, and the field lacks standardized benchmarks to make that choice systematically.
What We're Building
Our Spike Encoding Benchmark aims to provide: 1. Standardized test suite: 5 reference tasks spanning sensor fusion, image classification, keyword spotting, anomaly detection, and time-series prediction 2. Fair comparison framework: Same CMOS process target (28nm), same power budget, same area constraints 3. Open results database: Published encoding-vs-task performance data, accessible to the neuromorphic design community
The goal is not to declare a winner, but to give chip designers the data they need to make informed encoding choices for their specific application.
This technical note is part of Cmospike's Spike Encoding Benchmark research initiative.